1. Field of the Invention
The present invention relates to a layout design apparatus for designing a large scale integrated (LSI) chip layout, a layout design method, and a computer product.
2. Description of the Related Art
A conventional LSI chip layout begins with making a clock tree, followed by a wiring of a scan chain and then a timing convergence. This configuration increases working time for the timing convergence and hence it inevitably takes a long time to make the design. To cope with the problem, a structured application specific integrated circuit (ASIC) has recently been developed therein a pre-designed SCAN circuit and a built-in self test (BIST) circuit (see, for example, web site of Fujitsu, searched on Apr. 17th, 2004, http://pr.fujitsu.com/jp/news/2003/06/26.html).
However, If any one of such pre-designed circuits is not necessary to a user, and it is still left, unnecessary power is supplied to the circuit as well, resulting in a problem of extra power consumption. Furthermore, with increasingly complex and speedy circuits, it is difficult to lay out a clock tree with a small clock skew, and this also prolongs the design time.